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IDT74FCT833A/B FAST CMOS PARITY BUS TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
FAST CMOS PARITY BUS TRANSCEIVER
IDT74FCT833A/B
* Equivalent to AMD's Am29833 bipolar registers in pinout/ function, speed, and output drive over full temperature and voltage supply extremes * High-speed bidirectional bus transceiver for processororganized devices * IDT74FCT833A equivalent to Am29833 speed and output drive * IDT74FCT833B 30% faster than Am29833 * Buffered direction and 3-state controls * Error flag with open-drain output * IOL = 48mA * TTL input and output level compatible * CMOS output level compatible * Substantially lower input current levels than AMD's bilopar Am29800 series (5A max.) * Available in SOIC package
FEATURES:
The IDT74FCT833s are high-performance bus transceivers designed for two-way communications. They each contain an 8-bit data path from the R (port) to the T (port), an 8-bit data path from the T (port) to the R (port), and a 9-bit parity checker/generator. The error flag can be clocked and stored in a register and read at the ERR output. The clear (CLR) input is used to clear the error flag register. The output enables OET and OER are used to force the port outputs to the high-impedance state so that the device can drive bus lines directly. In addition, OER and OET can be used to force a parity error by enabling both lines simultaneously. This transmission of inverted parity gives the designer more system diagnostic capability. The devices are specified at 48mA output sink current over the commercial temperature range.
DESCRIPTION:
FUNCTIONAL BLOCK DIAGRAM
RI
8 8
TI
15
OET
14
PARITY
O ER
1
8
8
S
MUX
9
9-BIT PARITY TREE
10
D
Q Q
ERR
P CLK CLR
13
CP CLR
11
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
JULY 2000
DSC-4621/3
(c) 2000 Integrated Device Technology, Inc.
IDT74FCT833A/B FAST CMOS PARITY BUS TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
OER R0 R1 R2 R3 R4 R5 R6 R7 ERR CLR GND 1 2 3 4 5 6 7 8 9 10 11 12
SOIC TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Operating Temperature Temperature under BIAS Storage Temperature Power Dissipation DC Output Current Max -0.5 to +7 -0.5 to VCC 0 to +70 -55 to +125 -55 to +125 0.5 120 Unit V V C C C W mA
24 23 22 21 20 19 18 17 16 15 14 13
VCC T0 T1 T2 T3 T4 T5 T6 T7 PARITY OET CLK
VTERM(3) TA TBIAS TSTG PT IOUT
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Input and Vcc terminals only. 3. Output and I/O terminals only.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit pF pF
NOTE: 1. This parameter is measured at characterization but not tested.
ERROR FLAG OUTPUT FUNCTION PIN DESCRIPTION TABLE(1,2) Pin Name I/O
Inputs CLR H H H L CLK X Internal To Device Point "P" H X L X Output Pre-State ERRn-1 H L X X Output ERR H L L H Function Sample (1's Capture) Clear CLR TI PARITY OET CLK I I/O I/O I I OER RI ERR I I/O O
Description
RECEIVE enable input. 8-bit RECEIVE data input/output. Output from fault registers. Register detection of odd parity fault on rising clock edge (CLK). A registered ERR output remains LOW until cleared. Open drain output, requires pull up resistor. Clears the fault register output. 8-bit TRANSMIT data input/output. 1-bit PARITY output. TRANSMIT enable input. External clock pulse input for fault register flag.
NOTES: 1. OET is HIGH and OER is LOW. 2. H = HIGH L = LOW = LOW-to-HIGH transition of clock X = Don't Care
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IDT74FCT833A/B FAST CMOS PARITY BUS TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
FUNCTION TABLE(1)
Inputs TI Incl Parity OET L L L L H H H H X H H H H L L L L OER H H H H L L L L X H H H H L L L L CLR H H H H H H H H L H L H H H H H H CLK X H or L X RI ( or H's) H (Odd) H (Even) L (Odd) L (Even) NA NA NA NA X X X H or L (Odd) H or L (Even) H (Odd) H (Even) L (Odd) L (Even) ( of H's) NA NA NA NA H (Odd) H (Even) L (Odd) L (Even) X X X X X NA NA NA NA RI NA NA NA NA H H L L NA Z Z Z Z NA NA NA NA TI H H L L NA NA NA NA NA Z Z Z Z H H L L Parity L H L H NA NA NA NA NA Z Z Z Z H L H L ERR(2) H L H L H L H L H * H H L L H L H Function Transmit data from R Port to T Port with parity; receiving path is disabled. Receive data from T Port to R Port with parity test resulting in flag: transmitting path is disabled. Clear the state of error flag register. Both transmitting and receiving paths are disabled. Parity logic defaults to transmit mode. Forced-error checking. Outputs
NOTES: 1. H = HIGH Z = High-Impedance Odd = Odd number of logic one's L = LOW NA = Not Applicable Even = Even number of logic one's = LOW-to-HIGH transition of clock X = Don't Care I = 0, 1, 2, 3, 4, 5, 6, 7 * = No change to stored Error State 2. Output state assumes HIGH output pre-state.
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IDT74FCT833A/B FAST CMOS PARITY BUS TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V Commercial: TA = 0C to +70C, VCC = 5.0V 5%
Symbol VIH VIL IIH IIL IIH IIL VIK IOS VOH Parameter Input HIGH Level Input LOW Level Input HIGH Current (Except I/O Pins) Input LOW Current (Except I/O Pins) Input HIGH Current (I/O Pins Only) Input LOW Current (I/O Pins Only) Clamp Diode Voltage Short Circuit Current Output HIGH Voltage (Except ERR) Output LOW Voltage Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI =VCC VI = 2.7V VI = 0.5V VI = GND VCC = Max. VI = VCC VI = 2.7V VI = 0.5V VI = GND Vcc = Min., IN = -18mA Vcc = Max.(3), VO = GND Vcc = 3V, VIN = VLC or VHC, IOH = -32A Vcc = Min. IOH = -300A IOH = -24mA VIN = VIH or VIL Vcc = 3V, VIN = VLC or VHC, IOL = 300A Vcc = Min. Except IOL = 300A VIN = VIH ERR IOL = 48mA ERR IOL = 48mA or VIL Min. 2 -- -- -- -- -- -- -- -- -- -- -60 VHC VHC 2.4 -- -- -- -- Typ.(2) -- -- -- -- -- -- -- -- -- -- -0.7 -120 VCC VCC 4.3 GND GND 0.3 0.3 Max. -- 0.8 5 5(4) -5(4) -5 15 15(4) -15(4) -15 -1.2 -- -- -- -- VLC VLC(4) 0.5 0.5 Unit V V A
A
V mA V
VOL
V
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient and maximum loading. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not ttested.
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IDT74FCT833A/B FAST CMOS PARITY BUS TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC - 0.2V
Symbol ICC ICC ICCD Parameter Quiescent Power Supply Current Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Outputs Open Test Conditions(1) Vcc = Max.; VIN VHC, VIN VLC Vcc = Max. VIN = 3.4V(3) Vcc = Max. VIN VLC OET = OER = GND One Input Toggling 50% Duty Cycle Vcc = Max. Outputs Open fCP = 10MHz 50% Duty Cycle OET = GND OER = VCC fi = 2.5MHz One Bit Toggling Vcc = Max. Outputs Open fCP = 10MHz 50% Duty Cycle OET = GND fi = 2.5MHz OER = VCC Eight Bits Toggling Min. -- -- VIN VHC -- Typ.(2) 0.2 0.5 0.15 Max. 1.5 2 0.25 Unit mA mA mA/ MHz
IC
Total Power Supply Current(6)
VIN VHC VIN VLC (FCT) VIN = 3.4V VIN = GND
--
1.4
3.4
mA
--
1.9
5.4
VIN VHC VIN VLC (FCT) VIN = 3.4V VIN = GND
--
4
7.8(5)
--
6.2
16.8(5)
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for register devices (zero for non-register devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz.
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IDT74FCT833A/B FAST CMOS PARITY BUS TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT74FCT833A Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tREM tW tW tPHL tPLH tPLH tPHL Parameter Propagation Delay RI to TI, TI to RI Propagation Delay RI to PARITY Output Enable Time OER, OET to RI, TI Output Disable Time OER, OET to RI, TI TI, PARITY to CLK Set-up Time TI, PARITY to CLK Hold Time Clear Recovery Time CLR to CLK Clock Pulse Width HIGH or LOW Clear Pulse Width LOW Propagation Delay CLK to ERR Propagation Delay CLR to ERR Propagation Delay OER to PARITY CL = 50pF CL = 300pF(3) Conditions CL = 50pF CL = 300pF CL = 50pF CL = 300pF CL = 50pF
(3)
(1)
IDT74FCT833B Max. 10 17.5 15 22.5 12 19.5 10.7 12 -- -- -- -- -- 12 16 15 22.5 Min. -- -- -- -- -- -- -- -- 8.5 0 10.5 5.5 5.5 -- -- -- --
(2)
Min.
(2)
Max. 7 14.5 10.5 18 8.5 16 7.2 8.5 -- -- -- -- -- 8.5 15 10.5 18
Unit ns ns ns ns ns ns ns ns ns ns ns ns
-- -- -- -- -- -- -- -- 12 0 15 7 7 -- -- -- --
(3)
CL = 300pF(3) CL = 5pF(3) CL = 50pF CL = 50pF
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. These parameters are guaranteed but not tested.
6
IDT74FCT833A/B FAST CMOS PARITY BUS TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC 500 VIN Pulse Generator RT D.U.T . VOUT 7.0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low Switch Closed Open
50pF CL
500
All Other Tests
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Octal link
Test Circuits for All Outputs
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC.
tSU
tH
tREM
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
Octal link
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
Octal link
1.5V
1.5V
tSU
tH
Pulse Width
Set-Up, Hold, and Release Times
ENABLE SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
Octal link
DISABLE 3V 1.5V 0V 3.5V 0.3V tPHZ 0.3V 1.5V 0V VOH 0V
Octal link
CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 3.5V 1.5V tPLZ
VOL
Propagation Delay
Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; ZO 50; tF 2.5ns; tR 2.5ns.
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IDT74FCT833A/B FAST CMOS PARITY BUS TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX FCT XXXX Temp. Range Device Type X Package
SO
Small Outline IC
833A 833B
Parity Bus Transceiver
74
0C to +70C
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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